1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a circuit for preventing a system malfunction in a semiconductor memory and method thereof.
2. Discussion of the Related Art
FIG. 1 illustrates a system clock generation circuit according to the related art.
Referring to FIG. 1, a circuit for generating a system clock signal according to the related art comprises a resonator 100 generating an oscillating signal, an oscillator circuit 200 generating an oscillating clock signal CLK by receiving the oscillating signal, a noise filter 300 filtering a radio frequency component of the oscillating clock signal CLK, and a system clock generator 400 generating a plurality of system clock signals SCLK0, SCLK1 . . . using the filtered oscillating clock signal CLK. In this case, the resonator 100 is constructed with oscillating capacitors C1 and C2 and a crystal resonator Xtal.
The oscillating circuit 200 includes a transfer gate TG1 and an inverter IN1 connected between pins Xin and Xout in parallel, an NMOS transistor NM1 connected between an input terminal of the inverter IN1 and a ground to pull down the pin Xin, and a NOR gate NOR1 generating the oscillating clock signal CLK NORing a stop signal and NOR gate NOR1 generating the oscillating clock signal CLK NORing a stop signal and the oscillating signal. In this case, operation of the transfer gate TG1 is controlled by the stop signal.
Operation of the circuit for generating a system clock signal according to related art is explained by referring to the attached drawing as follows.
When the resonator 100, i.e. the oscillating capacitors C1 and C2 and crystal resonator Xtal, is connected between the pins Xin and Xout, the oscillating signal having a sine wave as shown in FIG. 2(A) is applied to the pin Xout. In this case, Vmin is approximately equal to 0 and Vmax is approximately equal to Vcc.
First of all, when a stop signal of high level is inputted, the oscillating circuit 200 is initialized.
When a stop signal of high level is inputted, the transfer gate TG1 is turned off and the NMOS transistor NM1 is turned on. Thus, the oscillating circuit 200 stops operating. In this case, pull-down operation of the turned-on NMOS transistor NM1 enables the pin Xin to maintain ground level, while the other pin Xout connected to the pin Xin through the inverter IN1 maintains a level equal to xe2x80x98Vccxe2x80x99.
With the above state, when a stop signal of low level is inputted, the oscillating circuit 200 carries out normal oscillating operation.
When the stop signal of high level is inputted, the transfer gate TG1 is turned on and the NMOS transistor NM1 is turned off. Thus, the oscillating signal outputted from the resonator 100 is inputted to one terminal of the NOR gate NOR1 through the pin Xout. The NOR gate NOR1 carries out NORing on the oscillating signal inputted to one terminal and the stop signal inputted to the other terminal and then outputs the oscillating clock signal CLK as shown in FIG. 2(B). In this case, a logic-threshold value of the NOR gate NOR1 is equal to xc2xd Vcc.
Therefore, the noise filter 300 removes the radio frequency component from the oscillating clock signal CLK generated from the oscillating circuit 200 and then outputs the filtered oscillating clock signal CLK to the system clock generator 400. The system clock generator 400 then generates a plurality of the system clock signals SCLK0 SCLK1 . . . using the filtered oscillating clock signal CLK.
Meanwhile, noise at the oscillating stage means that abnormality of frequency or amplitude of the oscillating signal occurs since a signal other than a normal oscillating signal is applied to the pin Xin or Xout. Besides, a radio frequency component of the oscillating signal is removed by the noise filter 300. Yet, a signal which is not the radio frequency signal, as shown in FIG. 2(A), results in increasing a minimum amplitude of the oscillating signal or decreasing a maximum amplitude of the oscillating signal. Specifically, such a variation of the amplitude is difficult to detect and cannot be removed by a certain circuit.
Therefore, when noise is applied to the pins Xin and Xout, the waveform of the oscillating signal is distorted as shown in FIG. 2. Thus, minimum and maximum amplitudes of the oscillating signal are changed. Such variations of the waveform cause alterations in the pulse width of the oscillating clock signal CLK. Consequently, such a pulse width variation also changes a duty of the system clock signal SCLK, thereby bringing about malfunctions in a system using the system clock signal SCLK inside an IC such as a CPU.
Accordingly, the present invention is directed to a circuit for preventing system malfunction in a semiconductor memory and method thereof that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a circuit for preventing system malfunction in a semiconductor memory and method thereof enabling prevention of system malfunction due to noise resulting from an oscillating stage.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a circuit for preventing system malfunction in a semiconductor memory according to the present invention includes an oscillating circuit generating an oscillating clock signal by receiving an oscillating signal, a system clock generator generating a system clock signal by receiving the oscillating clock signal, and a malfunction preventing unit resetting an inner system by sensing an amplitude variation of the oscillating signal wherein the amplitude variation is caused by noise.
In another aspect of the present invention, a method of preventing system malfunction in a semiconductor memory includes the steps of generating an oscillating clock signal by receiving an oscillating signal, generating a system clock signal using the oscillating clock signal, sensing an amplitude variation of the oscillating signal wherein the amplitude variation is caused by noise, and resetting an inner system when an amplitude of the oscillating signal is out of a predetermined range.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.